1. Field of the Invention
The present invention relates to a method of making semiconductor memory elements, and more particularly to a method of making semiconductor memory elements such as in dynamic random access memories enabling simplified manufacture and increased capacitor area.
2. Description of the Prior Art
The development of manufacturing techniques for semiconductor elements has promoted the development of dynamic random access memories (DRAMs) of high capacitance as semiconductor memory elements. While early DRAMs had a planar structure, DRAMs have been transfigured to have three-dimensional storage capacitors with a stack or trench structure so as to maximize area efficiency. Recently, highly integrated DRAM cells primarily utilize stack structures because of the ease of manufacturing stack structures.
However, conventional stack-type DRAM cells have a limitation on the increase in capacitor are in that the bit lines of such cells typically are formed after the formation of transistors and capacitors, thus requiring area for contacting the bit lines with source/drain regions. Due to the provision of bit line contacts, such cells also are limited in the increase in storage node height, and thereby are limited on the possible increase in storage node area.
For solving these problems, a stack type DRAM cell capable of increasing the storage node area has been developed. In manufacturing such a DRAM cell, formation of the bit line and transistor precede the formation of the capacitor so that a storage node may be formed to extend to the bit line contact region.
FIGS. 1a to 1e are sectional views illustrating a method of making a semiconductor memory element having a crown type capacitor structure.
First, a process for forming a transistor of the semiconductor memory element will be described in conjunction with FIG. 1a. In accordance with this process, field oxide film 2 is first formed over semiconductor substrate 1, so as to define active regions. Over the surface thereof and over field oxide film 2, gate oxide film 3 is formed and a polysilicon film is deposited. The polysilicon film is in turn coated with photoresist and then subjected to photoetching so as to form a photoresist pattern defining gate regions. Using the photoresist pattern, the polysilicon film is etched to form gates 4. Thereafter, substrate 1 is then subjected to an impurity ion implantation to form source and drain regions 5. Over the resultant entire exposed surface, oxide film 6 is then deposited, so as to form transistors.
Referring to FIG. 1b, there is illustrated a process for forming a bit line. For forming a bit line contact, oxide film 6 partially is removed at portions at which a bit line is to be formed. Over the resultant entire exposed surface, doped polysilicon film 7 for the bit line is deposited, which is then subjected to an etch-back process for providing a smoothed surface.
Over smoothed polysilicon film 7 are deposited tungsten silicide (WSi.sub.2) film 8 and oxide film 9 in this order. Thereafter, polysilicon film 7, tungsten silicide film 8 and oxide film 9 are subjected to patterning for formation of the bit line. After formation of the bit line, another oxide film is deposited over the resultant entire exposed surface and then subjected to an anisotropic dry etching process so that side wall spacers 10 are formed at opposite side surfaces of the bit line as illustrated in FIG. 1b. Side wall spacers 10 are oxide films for isolating the bit line from the storage and plate nodes of a capacitor to be formed in subsequent steps.
After completing the formation of the bit line as shown in FIG. 1b, semiconductor substrate has capacitor contacts 11 exposed in a self-aligned manner.
FIG. 1c illustrates plug forming and smoothing processes. As shown in FIG. 1c, a selective growth of a polysilicon film is carried out for forming plugs 12 only on capacitor contacts 11. Over the resultant entire exposed surface is coated nitride film 13, which is then subjected to etch-back and smoothing processes. Thereafter, oxide film 14 is formed over smoothed nitride film 13.
Referring to FIGS. 1d and 1e, a process for forming a capacitor will be described. First, both oxide film 14 and nitride film 13 are subjected to an anisotropic etching with a high etch selectivity so that these films remain only at portions disposed over the bit line and field oxide film, as shown in FIG. 1d. Subsequently, doped polysilicon film 15 for a storage node is deposited over the resultant entire exposed surface.
Over doped polysilicon film 15 is deposited another oxide film (not shown), which is, in turn, subjected to etch-back and smoothing processes so that portions of polysilicon film 15 on oxide film 14 are exposed. Using smoothed oxide film 14 as a mask, polysilicon film 15 is then etched back to remove portions thereof disposed on oxide film 14 so that oxide film 14 is exposed for forming a storage node, as shown in FIG. le. As the storage node is formed by etching the portion of polysilicon film 15 disposed on oxide film 14, it is separated from other storage nodes of neighboring cells. The storage node is disposed above the bit line and connected with source and drain regions 5 via plugs 12.
After formation of the storage node, exposed oxide film 14 is removed using a wet etching process. Over the resultant entire exposed surface, tantalum oxide film (Ta.sub.2 O.sub.5) 16 is then formed so as to provide a dielectric film. Finally, a tungsten film is deposited over dielectric tantalum oxide film 16 so as to form plate node 17. Thus, a DRAM cell is produced. Such a conventional semiconductor memory element has a storage node having a single side wall structure as shown in FIG. 1e.
However, the above-described method of making a semiconductor memory element is complex in that it includes processes for forming nitride and oxide films and then patterning by anisotropically dry etching the films with a high etch selectivity so as to increase the height of the storage node of the capacitor, and also in that it includes a process for selectively forming a polysilicon plug at the capacitor contact so as to smooth the nitride film.